Various types of semiconductor devices and techniques for manufacturing the semiconductor devices are known. For example, the U.S. Pat. No. 5,053,838 discloses a power IC and the manufacturing method thereof, U.S. Pat. No. 4,959,699 and U.S. Pat. No. 5,008,725 disclose vertical MOSFETs and the manufacturing methods thereof, U.S. Pat. No. 4,364,073 and U.S. Pat. No. 5,034,336 disclose vertical IGBTs and the manufacturing methods thereof, and U.S. Pat. No. 5,191,396 and U.S. Pat. No. 5,162,883 disclose a lateral MOSFET, lateral IGBT and the manufacturing methods thereof.
As a typical example of the prior art, the structure of an IC portion of the power IC disclosed in the U.S. Pat. No. 5,053,838 and the manufacturing method thereof are shown in FIGS. 42 to 48 and will be described with reference to certain process steps.
STEP(1): Referring now to FIG. 42, a first insulation film 3 of about 1000 nm in thickness is formed by thermally oxidizing an n-type semiconductor layer 2, doped with phosphorus at around 1.times.10.sup.16 cm.sup.-3, in steam at 1100.degree. C. for 3 hours.
STEP(2): As shown in FIG. 43, windows 4 are formed by selectively etching the predetermined parts of the first insulation film 3 by hydrofluoric acid etc. by using for masking a photoresist film patterned by photolithography.
STEP(3): Boron ions are then implanted at the dose amount of 2.times.10.sup.13 cm.sup.-3 in the surface layer of the n-type semiconductor layer 2 through the windows 4 at the acceleration voltage of 100 keV. STEP(4): Referring now to FIG. 44, the boron ions are diffused by heat treatment at 1100.degree. C. for 3 hours to form p-type regions 5 in the surface layer of the n-type semiconductor layer 2. STEP(5): Subsequently to this, steam oxidation is conducted at 1100.degree. C. for 80 min to form second insulation films 61 of thermally oxidized silicon of around 650 nm in thickness. The second insulation films 61, used for inter-layer insulation of wiring in the ICs or for field plates of the power devices, need not be formed precisely in the thickness thereof.
STEP(6): As shown in FIG. 45, the predetermined parts of the first and second insulation films are simultaneously etched away by hydrofluoric acid etc. by using a photoresist film patterned by photolithography for masking.
STEP(7): Third insulation films 7 of oxide of about 50 nm in thickness are then formed, for example, by dry oxidation at 1000.degree. C. for 30 min.
STEP(8): Referring now to FIG. 46, a poly-crystalline silicon film is deposited to a thickness of 500 nm by CVD. Phosphorus ions are implanted at the acceleration voltage of 100 keV to the poly-crystalline silicon film at the dose amount of 5.times.10.sup.15 cm.sup.-2. The implanted phosphorus ions are activated by heat treatment at 1000.degree. C. for 10 min. Gate electrodes 8 are formed by selectively etching the poly-crystalline silicon film by using a photoresist film patterned by photolithography for masking.
STEP(9): Then, heavily doped n-type regions 9 are formed in the surface layers of the n-type substrate 2 and a p-type region by implanting arsenic ions at the dose amount of 5.times.10.sup.15 cm.sup.-2 at the acceleration voltage of 150 keV by using for masking a photoresist film 15 patterned by photolithography, the first insulation films 3 and the gate electrodes 8.
STEP(10): As shown in FIG. 47, a fourth insulation film 10 of BPSG film of about 1000 nm in thickness is formed by CVD etc.
STEP(11): Contact holes 11, which reach the p-type regions 5 and the heavily doped n-type regions 9 through the fourth insulation film 10, are formed by selectively etching the BPSG film by using a photoresist film patterned by photolithography for masking as illustrated in FIG. 48.
STEP(12): Finally, metal electrodes 12 are formed by selectively etching an Al--Si--Cu film, deposited to a thickness of about 1000 nm by sputtering etc., by using a photoresist film patterned by photolithography for masking.
The semiconductor device 1 manufactured by the above process comprises a p-channel MOSFET further comprising a back gate electrode 12(PB), a source electrode 12(PS), a gate electrode 8(PG), and a drain electrode 12(PD); and an n-channel MOSFET further comprising a back gate electrode 12(NB), a source electrode 12(NS), a gate electrode 8(NG), and a drain electrode 12(ND). The illustrated device structure facilitates obtaining CMOS-ICs. The manufacturing method described above, however, includes ten photo-processing steps.
It is therefore necessary to reduce the photo-processing steps for reducing the manufacturing cost of the semiconductor devices. Accordingly, it is an object of the invention to provide a semiconductor device that has the same structure and exhibits the same performance with those of the conventional device and to provide a method of manufacturing the semiconductor device that reduces one step from the conventional photo-processing steps and facilitates reducing the cost of the semiconductor device.